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| M Features * * * * * * * * * * * * * * Full Differential Inputs MCP3302: 2 Differential or 4 Single ended Inputs MCP3304: 4 Differential or 8 Single ended Inputs 1 LSB max DNL 1 LSB max INL (MCP3302/04-B) 2 LSB max INL (MCP3302/04-C) Single supply operation: 2.7V to 5.5V 100 ksps sampling rate with 5V supply voltage 50 ksps sampling rate with 2.7V supply voltage 50 nA typical standby current, 1 A max 450 A max active current at 5V Industrial temp range: -40C to +85C 14 and 16-pin PDIP, SOIC and TSSOP packages MXDEVTM Evaluation kit available MCP3302/04 General Description The Microchip Technology Inc. MCP3302/04 13-bit A/D converters feature full differential inputs and low power consumption in a small package that is ideal for battery powered systems and remote data acquisition applications. The MCP3302 is programmable to provide two differential input pairs or four single ended inputs. The MCP3304 is programmable and provides four differential input pairs or eight single ended inputs. Incorporating a successive approximation architecture with on-board sample and hold circuitry, these 13-bit A/D converters are specified to have 1 LSB Differential Nonlinearity (DNL); 1 LSB Integral Nonlinearity (INL) for B-grade and 2 LSB for C-grade devices. The industry-standard SPITM serial interface enables 13-bit A/D converter capability to be added to any PICmicro(R) microcontroller. The MCP3302/04 devices feature low current design that permits operation with typical standby and active currents of only 50 nA and 300 A, respectively. The devices operate over a broad voltage range of 2.7V to 5.5V and are capable of conversion rates of up to 100 ksps. The reference voltage can be varied from 400 mV to 5V, yielding input-referred resolution between 98 V and 1.22 mV. 13-Bit Differential Input, Low Power A/D Converter with SPITM Serial Interface Applications * Remote Sensors * Battery Operated Systems * Transducer Interface Package Types PDIP, SOIC, TSSOP CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN The MCP3302 is available in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3304 is available in 16-pin PDIP and 150 mil SOIC packages. The full differential inputs of these devices enable a wide variety of signals to be used in applications such as remote data acquisition, portable instrumentation and battery operated applications. MCP3302 PDIP, SOIC CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND 2002 Microchip Technology Inc. MCP3304 DS21697B-page 1 MCP3302/04 Functional Block Diagram VREF VDD AGND DGND CH0 CH1 Input Channel Mux CDAC Comparator 13-Bit SAR + CH7* Sample & Hold Circuits - Control Logic Shift Register CS/SHDN DIN CLK DOUT * Channels 5-7 available on MCP3304 Only DS21697B-page 2 2002 Microchip Technology Inc. MCP3302/04 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name CH0-CH7 DGND CS/SHDN DIN DOUT CLK AGND VREF VDD Analog Inputs Digital Ground Chip Select / Shutdown Input Serial Data In Serial Data Out Serial Clock Analog Ground Reference Voltage Input +2.7V to 5.5V Power Supply Function Maximum Ratings* VDD........................................................................ 7.0V All inputs and outputs w.r.t. VSS .....-0.3V to VDD +0.3V Storage temperature .......................... -65C to +150C Ambient temp. with power applied ..... -65C to +125C Maximum Junction Temperature ....................... 150C ESD protection on all pins (HBM)......................... > 4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40C to +85C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Conversion Rate Maximum Sampling Frequency Conversion Time Acquisition Time DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Positive Gain Error Negative Gain Error Offset Error Note 1: 2: 3: 4: 5: 6: 7: 8: INL DNL -- -- -- -3 -3 -3 12 data bits + sign 0.5 1 0.5 -0.75 -0.5 +3 1 2 1 +2 +2 +6 bits LSB LSB LSB LSB LSB LSB MCP3302/04-B MCP3302/04-C Monotonic over temperature FSAMPLE TCONV TACQ -- -- -- -- 13 1.5 100 50 ksps ksps CLK periods CLK periods Note 8 VDD = VREF = 2.7V, VCM =1.35V Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5VP-P 500 mV @ 1 kHz, see test circuit Figure 3-3. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz TSSOP devices are only specified at 25C and +85C. For slow sample rates, see Section 6.2.1 for limitations on clock frequency. 2002 Microchip Technology Inc. DS21697B-page 3 MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40C to +85C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Common Mode Rejection Channel to Channel Crosstalk Power Supply Rejection Reference Input Voltage Range Current Drain Analog Inputs Full Scale Input Span Absolute Input Voltage Leakage Current Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance Note 1: 2: 3: 4: 5: 6: 7: 8: VIH VIL VOH VOL ILI ILO CIN, C OUT Binary Two's Complement 0.7 VDD -- 4.1 -- -10 -10 -- -- -- -- -- -- -- -- -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD TAMB = 25C, F = 1 MHz, Note 1 RS CSAMPLE CH0 - CH7 CH0 - CH7 -V REF -0.3 -- -- -- -- -- 0.001 1 25 VREF VDD + 0.3 1 -- -- V V A k pF See Figure 6-3 See Figure 6-3 0.4 -- -- -- 100 0.001 VDD 150 3 V A A Note 2 CS = VDD = 5V THD SINAD SFDR CMRR CT PSR -- -- -- -- -- -- -91 78 92 79 > -110 74 -- -- -- -- -- -- dB dB dB dB dB dB Note 3 Note 3 Note 3 Note 6 Note 6 Note 4 Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5VP-P 500 mV @ 1 kHz, see test circuit Figure 3-3. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz TSSOP devices are only specified at 25C and +85C. For slow sample rates, see Section 6.2.1 for limitations on clock frequency. DS21697B-page 4 2002 Microchip Technology Inc. MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40C to +85C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Timing Specifications: Clock Frequency (Note 8) Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data In Setup time Data In Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements: Operating Voltage Operating Current Standby Current Temperature Ranges: Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistance: Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-PDIP Thermal Resistance, 16L-SOIC Note 1: 2: 3: 4: 5: 6: 7: 8: JA JA JA JA JA -- -- -- -- -- 70 108 100 70 90 -- -- -- -- -- C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +85 +85 +150 C C C VDD IDD IDDS 2.7 -- -- -- -- 300 200 0.05 5.5 450 -- 1 V A A VDD , VREF = 5V, DOUT unloaded VDD , VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V FCLK THI TLO TSUCS TSU THD TDO TEN TDIS TCSH TR TF 0.105 0.105 210 210 100 50 -- -- -- -- 475 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.1 1.05 -- -- -- -- 50 125 200 125 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns See test circuits, Figure 3-1 Note 1 See test circuits, Figure 3-1 Note 1 VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 See test circuits, Figure 3-1 Note 1 VDD = 5V, FSAMPLE = 100 ksps VDD = 2.7V, FSAMPLE = 50 ksps Note 5 Note 5 Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5VP-P 500 mV @ 1 kHz, see test circuit Figure 3-3. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz TSSOP devices are only specified at 25C and +85C. For slow sample rates, see Section 6.2.1 for limitations on clock frequency. 2002 Microchip Technology Inc. DS21697B-page 5 MCP3302/04 . TCSH CS TSUCS THI CLK TSU DIN THD TLO MSB IN TEN TDO Null Bit Sign BIT TR TF LSB TDIS DOUT FIGURE 1-1: Timing Parameters DS21697B-page 6 2002 Microchip Technology Inc. MCP3302/04 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. . Note: . 1 0.8 0.6 0.4 Positive INL 1 0.8 0.6 0.4 VDD=V REF=2.7V Positive INL INL (LSB) INL (LSB) Negative INL 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 50 100 150 200 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10 20 30 40 50 60 70 Negative INL Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: vs. Sample Rate 2 1.5 1 Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V) . 2 1.5 1 Positive INL VDD = 2.7V Positive INL INL (LSB) 0 -0.5 -1 -1.5 -2 0 1 2 3 4 5 Negative INL INL(LSB) 0.5 0.5 0 -0.5 -1 -1.5 -2 0 0.5 1 Negative INL VREF(V) VREF(V) 1.5 2 2.5 3 FIGURE 2-2: vs. VREF. 1 0.8 0.6 0.4 Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V) 1 0.8 0.6 0.4 VDD=VREF=2.7V FSAMPLE = 50 ksps INL (LSB) 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 INL (LSB) 0.2 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). 2002 Microchip Technology Inc. DS21697B-page 7 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 1 0.8 0.6 0.4 Positive INL 1 0.8 0.6 0.4 VDD=VREF=2.7V FSAMPLE = 50 ksps Positive INL INL (LSB) INL (LSB) Negative INL 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 Negative INL Temperature(C) Temperature (C) FIGURE 2-7: vs. Temperature. 1 0.8 0.6 0.4 Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 1 0.8 0.6 VDD=VREF=2.7V Positive DNL 0.4 Positive DNL DNL (LSB) DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 50 100 150 200 Negative DNL 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10 20 30 40 50 60 70 Negative DNL Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. 2 1.5 1 FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 2 1.5 1 VDD=2.7V FSAMPLE = 50 ksps DNL(LSB) 0 -0.5 -1 -1.5 -2 0 1 2 3 4 5 6 Negative DNL DNL (LSB) 0.5 Positive DNL 0.5 0 -0.5 -1 -1.5 -2 Positive DNL Negative DNL VREF(V) 0 0.5 1 VREF (V) 1.5 2 2.5 3 FIGURE 2-9: (DNL) vs. VREF. Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).] DS21697B-page 8 2002 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 1 0.8 0.6 0.4 1 0.8 0.6 0.4 VDD=V REF=2.7V FSAMPLE = 50 ksps DNL (LSB) DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code Code FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). 1 0.8 0.6 1 0.8 0.6 0.4 Positive DNL VDD=V REF=2.7V FSAMPLE = 50 ksps Positive DNL 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 Negaitive DNL DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 Negative DNL Temperature (C) Temperature (C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. 4 3 FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 20 18 16 Positive Gain Error (LSB) Offset Error (LSB) 2 1 0 -1 -2 -3 0 1 2 3 4 5 6 VDD =5V FSAMPLE = 100 ksps 14 12 10 8 6 4 2 0 0 VDD = 2.7V FSAMPLE = 50 ksps VDD = 5V FSAMPLE = 100 ksps 1 2 3 4 5 6 VREF(V) VREF(V) FIGURE 2-15: VREF. Positive Gain Error vs. FIGURE 2-18: Offset Error vs. VREF. 2002 Microchip Technology Inc. DS21697B-page 9 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 0 -0.2 3.5 3 VDD=VREF=5V FSAMPLE = 100 ksps Positive Gain Error (LSB) Offset Error (LSB) -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -50 0 50 VDD=V REF=2.7V FSAMPLE = 50 ksps VDD=VREF=5V FSAMPLE = 100 ksps 2.5 2 1.5 1 0.5 0 -50 0 50 100 150 VDD=VREF=2.7V FSAMPLE = 50 ksps 100 150 Temperature (C) Temperature (C) FIGURE 2-19: Temperature. 100 90 80 70 Positive Gain Error vs. FIGURE 2-22: Temperature. 90 Offset Error vs. VDD=VREF=5V FSAMPLE = 100 ksps 80 70 SNR (db) 60 50 40 30 20 10 0 1 10 SINAD (dB) VDD=VREF=2.7V FSAMPLE = 50 ksps 60 50 40 30 20 10 0 VDD=V REF=2.7V FSAMPLE = 50 ksps VDD=V REF=5V FSAMPLE = 100 ksps 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency. 0 -10 -20 -30 VDD=VREF=2.7V FSAMPLE = 50 ksps FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency. 80 70 60 THD (dB) -40 -50 -60 -70 -80 -90 -100 1 VDD=VREF=5V FSAMPLE = 100 ksps SINAD (dB) 50 40 30 20 10 0 VDD=V REF=2.7V FSAMPLE = 50 ksps VDD=VREF=5V FSAMPLE = 100 ksps 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level. DS21697B-page 10 2002 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 13 12.8 12.6 VDD=VREF=5V FSAMPLE = 100 ksps VDD=VREF=2.7V FSAMPLE = 50 ksps 13 12 11 10 9 8 7 0 1 2 3 4 5 VDD=2.7V FSAMPLE = 50 ksps VDD=5V FSAMPLE = 100 ksps ENOB (rms) ENOB (rms) 12.4 12.2 12 11.8 11.6 11.4 11.2 1 10 100 VREF(V) Input Frequency (kHz) FIGURE 2-25: (ENOB) vs. VREF. 100 90 80 70 Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. -30 -35 -40 -45 0.1 F Bypass Capacitor VDD=VREF=5V FSAMPLE = 100 ksps SFDR (dB) 50 40 30 20 10 0 1 VDD=V REF=2.7V FSAMPLE = 50 ksps PSR(dB) 10 100 60 -50 -55 -60 -65 -70 -75 -80 1 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10000 20000 30000 40000 50000 FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 5000 10000 15000 20000 25000 Frequency (Hz) Amplitude (dB) Amplitude (dB) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz Input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz Input (Representative Part, VDD = 2.7V). 2002 Microchip Technology Inc. DS21697B-page 11 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 120 100 80 450 400 350 300 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 IREF (A) IDD (A) 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) VDD (V) FIGURE 2-31: 600 500 400 300 200 IDD vs. VDD. FIGURE 2-34: 120 IREF vs. VDD. VDD=VREF =5V 100 80 VDD=V REF=5V IREF (A) IDD (A) 60 40 VDD=VREF =2.7V 100 0 0 50 100 150 200 20 0 0 50 VDD=V REF=2.7V 100 150 200 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-32: 400 350 300 IDD vs. Sample Rate. FIGURE 2-35: 100 90 IREF vs. Sample Rate. IDD (A) 200 150 100 50 0 -50 0 50 100 150 VDD=V REF=2.7V FSAMPLE = 50 ksps IREF (A) 250 V DD=VREF=5V FSAMPLE = 100 ksps 80 70 60 50 40 30 20 10 0 -50 0 50 VDD=VREF=5V FSAMPLE = 100 ksps VDD=VREF=2.7V FSAMPLE = 50 ksps 100 150 Temperature (C) Temperature (C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature. DS21697B-page 12 2002 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25C. 2 1.5 80 70 60 Negative Gain Error (LSB) 1 0.5 0 -0.5 -1 -1.5 -2 VDD=V REF=2.7V FSAMPLE = 50 ksps VDD=VREF=5V FSAMPLE = 100 ksps IDDS (pA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 6 -50 0 50 100 150 VDD (V) Temperature (C) FIGURE 2-37: 100 IDDS vs. VDD. FIGURE 2-40: Temperature. 80 Common Mode Rejection Ration(dB) Negative Gain Error vs. 10 79 78 77 76 75 74 73 72 71 70 1 10 100 Input Frequency (kHz) 1000 IDDS (nA) 1 0.1 0.01 0.001 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-38: 4 3.5 IDDS vs. Temperature. FIGURE 2-41: vs. Frequency. Common Mode Rejection Negative Gain Error (LSB) 3 2.5 2 1.5 1 0.5 0 -0.5 -1 0 1 2 3 4 5 6 VDD=5V FSAMPLE = 100 ksps VREF (V) FIGURE 2-39: Negative Gain Error vs. Reference Voltage. 2002 Microchip Technology Inc. DS21697B-page 13 MCP3302/04 3.0 TEST CIRCUITS 1 k 1/2 MCP602 + 5V 500 mVP-P To V DD on DUT 1.4V MCP330X DOUT 3 k Test Point 2.63V 20 k 5VP-P - 1 k 1 k CL = 100 pF FIGURE 3-1: Test Point Load Circuit for TR, TF, TDO. FIGURE 3-3: Power Supply Sensitivity Test Circuit (PSRR). VREF = 5V VDD = 5V 0.1 F VDD MCP330X DOUT 3 k 100 pF VSS VDD /2 TDIS Waveform 2 TEN Waveform TDIS Waveform 1 5VP-P 1 F 0.1 F IN(+) IN(-) 5VP-P VREF VDD MCP330X VSS Voltage Waveforms for TDIS CS VIH 90% TDIS VCM = 2.5V DOUT Waveform 1* FIGURE 3-4: Full Differential Test Configuration Example. DOUT Waveform 2 10% VREF = 2.5V 1F 0.1F 5VP-P VREF VDD MCP330X IN(-) VSS IN(+) VDD = 5V 0.1F *Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 3-2: TEN. Load circuit for TDIS and VCM = 2.5V FIGURE 3-5: Pseudo Differential Test Configuration Example. DS21697B-page 14 2002 Microchip Technology Inc. MCP3302/04 4.0 PIN DESCRIPTIONS 4.6 Serial Clock (CLK) The descriptions of the pins are listed in Table 4-1. The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. See Figure 7-2 for serial communication protocol. TABLE 4-1: Name CH0-CH7 DGND CS/SHDN DIN DOUT CLK AGND VREF VDD PIN FUNCTION TABLE Function Analog Inputs Digital Ground Chip Select / Shutdown Input Serial Data In Serial Data Out Serial Clock Analog Ground Reference Voltage Input +2.7V to 5.5V Power Supply 4.7 AGND Ground connection to internal analog circuitry. To ensure accuracy, this pin must be connected to the same ground as DGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 6.6 for more information regarding circuit layout. 4.8 Voltage Reference (VREF) 4.1 CH0-CH7 This input pin provides the reference voltage for the device, which determines the maximum range of the analog input signal and the LSB size. The LSB size is determined according to the equation shown below. As the reference input is reduced, the LSB size is reduced accordingly. Analog input channels. These pins have an absolute voltage range of VSS - 0.3V to VDD + 0.3V. The full scale differential input range is defined as the absolute value of (IN+) - (IN-). This difference can not exceed the value of VREF - 1 LSB or digital code saturation will occur. EQUATION LSB Size = 2 x VREF 8192 4.2 DGND Ground connection to internal digital circuitry. To ensure accuracy this pin must be connected to the same ground as AGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 6.6 for more information regarding circuit layout. When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the accuracy of the ADC conversion results. 4.3 Chip Select/Shutdown (CS/SHDN) 4.9 VDD The CS/SHDN pin is used to initiate communication with the device when pulled low. This pin will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions and cannot be tied low for multiple conversions. See Figure 7-2 for serial communication protocol. The voltage on this pin can range from 2.7 to 5.5V. To ensure accuracy, a 0.1 F ceramic bypass capacitor should be placed as close as possible to the pin. See Section 6.6 for more information regarding circuit layout. 4.4 Serial Data Input (D IN) The SPI port serial data input pin is used to clock in input channel configuration data. Data is latched on the rising edge of the clock. See Figure 7-2 for serial communication protocol. 4.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure 7-2 for serial communication protocol. 2002 Microchip Technology Inc. DS21697B-page 15 MCP3302/04 5.0 DEFINITION OF TERMS Bipolar Operation - This applies to either a differential or single ended input configuration, where both positive and negative codes are output from the A/D converter. Full bipolar range includes all 8192 codes. For bipolar operation on a single ended input signal, the A/D converter must be configured to operate in pseudo differential mode. Unipolar Operation - This applies to either a single ended or differential input signal where only one side of the device transfer is being used. This could be either the positive or negative side, depending on which input (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. Full Differential Operation - Applying a full differential signal to both the IN(+) and IN(-) inputs is referred to as full differential operation. This configuration is described in Figure 3-4. Pseudo-Differential Operation - Applying a single ended signal to only one of the input channels with a bipolar output is referred to as pseudo differential operation. To obtain a bipolar output from a single ended input signal the inverting input of the A/D converter must be biased above VSS. This operation is described in Figure 3-5. Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipolar transfer function is defined as the maximum integral nonlinearity error. The endpoints of the transfer function are a point 1/2 LSB above the first code transition (0x1000) and 1/2 LSB below the last code transition (0x0FFF). Differential Nonlinearity - The difference between two measured adjacent code transitions and the 1 LSB ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the last positive code transition (0x0FFF) and the ideal voltage level of VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal voltage level of -VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2 LSB voltage level. Acquisition Time - The acquisition time is defined as the time during which the internal sample capacitor is charging. This occurs for 1.5 clock cycles of the external CLK as defined in Figure 7-2. Conversion Time - The conversion time occurs immediately after the acquisition time. During this time, successive approximation of the input signal occurs as the 13-bit result is being calculated by the internal circuitry. This occurs for 13 clock cycles of the external CLK as defined in Figure 7-2. DS21697B-page 16 Signal to Noise Ratio - Signal to Noise Ratio (SNR) is defined as the ratio of the signal to noise measured at the output of the converter. The signal is defined as the rms amplitude of the fundamental frequency of the input signal. The noise value is dependant on the device noise as well as the quantization error of the converter and is directly affected by the number of bits in the converter. The theoretical signal to noise ratio limit based on quantization error only for an N-bit converter is defined as: EQUATION SNR = ( 6.02N + 1.76 )dB For a 13-bit converter, the theoretical SNR limit is 80.02 dB. Total Harmonic Distortion - Total Harmonic Distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental, measured at the output of the converter. For the MCP3302/04, it is defined using the first 9 harmonics, as is shown in the following equation: EQUATION V 2 + V 3 + V 4 + ..... + V 8 + V 9 THD(-dB) = -20 log -------------------------------------------------------------------------2 V1 Here V 1 is the rms amplitude of the fundamental and V2 through V9 are the rms amplitudes of the second through ninth harmonics. Signal to Noise plus Distortion (SINAD) - Numerically defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic performance of the converter, including any harmonic distortion. 2 2 2 2 2 EQUATION SINAD(dB) = 20 log 10 ( SNR 10 ) + 10 - ( THD 10 ) EffectIve Number of Bits - Effective Number of Bits (ENOB) states the relative performance of the ADC in terms of its resolution. This term is directly related to SINAD by the following equation: EQUATION SINAD - 1.76 ENOB ( N ) = ---------------------------------6.02 For SINAD performance of 78 dB, the effective number of bits is 12.66. Spurious Free Dynamic Range - Spurious Free Dynamic Range (SFDR) is the ratio of the rms value of the fundamental to the next largest component in ADC's output spectrum. This is, typically, the first harmonic, but could also be a noise peak. 2002 Microchip Technology Inc. MCP3302/04 6.0 6.1 APPLICATIONS INFORMATION Conversion Description 6.2 Driving the Analog Input The MCP3302/04 A/D converters employ a conventional SAR architecture. With this architecture, the potential between the IN+ and IN- inputs are simultaneously sampled and stored with the internal sample circuits for 1.5 clock cycles. Following this sampling time, the input hold switches of the converter open and the device uses the collected charge to produce a serial 13-bit binary two's complement output code. This conversion process is driven by the external clock and must include 13 clock cycles, one for each bit. During this process, the most significant bit (MSB) is output first. This bit is the sign bit and indicates if the IN+ or INinput is at a higher potential. The analog input of the MCP3302/04 is easily driven, either differentially or single ended. Any signal that is common to the two input channels will be rejected by the common mode rejection of the device. During the charging time of the sample capacitor, a small charging current will be required. For low source impedances, this input can be driven directly. For larger source impedances, a larger acquisition time will be required due to the RC time constant that includes the source impedance. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 13-bit accurate voltage level during the 1.5 clock cycle acquisition period. An analog input model is shown in Figure 6-3. This model is accurate for an analog input, regardless if it is configured as a single ended input, or the IN+ and INinput in differential mode. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance with no additional acquisition time increases the offset, gain and integral linearity errors of the conversion. To overcome this, a slower clock speed can be used to allow for the longer charging time. Figure 6-2 shows the maximum clock speed associated with source impedances. IN+ Hold CSAMP + - CDAC Comp 13-Bit SAR INHold CSAMP Shift Register DOUT FIGURE 6-1: Simplified Block Diagram. Maximum Clock Frequency (MHz) 2.5 2.0 1.5 1.0 0.5 0.0 100 1000 10000 100000 Source Resistance (ohms) FIGURE 6-2: Maximum Clock Frequency vs. Source Resistance (RS) to maintain 1 LSB INL. 2002 Microchip Technology Inc. DS21697B-page 17 MCP3302/04 VDD RSS CHx VT = 0.6V Sampling Switch SS RS = 1 k C SAMPLE = DAC capacitance = 25 pF VSS Legend VA = signal source RSS = source impedance CHx = input channel pad CPIN = input pin capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions SS = sampling switch RS = sampling switch resistor CSAMPLE = sample/hold capacitance VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA FIGURE 6-3: 6.2.1 Analog Input Model. MAINTAINING MINIMUM CLOCK SPEED When the MCP3302/04 initiates, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. For the MCP330X devices, the recommended minimum clock speed during the conversion cycle (TCONV) is 105 kHz. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met. bring down the high pass corner. The value of R will need to be 1 k, or less, since higher input impedances require additional acquisition time. Using the RC values in Figure 6-4, we have a 100 Hz corner frequency. See Figure 2-12 for relation between input impedance and acquisition time. VDD = 5V 0.1 F C 10 F VIN 1 k R IN+ INMCP330X VREF 6.3 Biasing Solutions VOUT 1 F VIN 0.1 F MCP1525 For pseudo-differential bipolar operation, the biasing circuit (shown in Figure 6-4) shows a single ended input AC coupled to the converter. This configuration will give a digital output range of -4096 to +4095. With the 2.5V reference, the LSB size equal to 610 V. Although the ADC is not production tested with a 2.5V reference as shown, linearity will not change more than 0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and INL errors versus VREF at VDD = 5V. A trade-off exists between the high pass corner and the acquisition time. The value of C will need to be quite large in order to FIGURE 6-4: Pseudo-differential biasing circuit for bipolar operation. Using an external operation amplifier on the input allows for gain and also buffers the input signal from the input to the ADC allowing for a higher source impedance. This circuit is shown in Figure 6-5. DS21697B-page 18 2002 Microchip Technology Inc. MCP3302/04 6.4 VDD = 5V 10 k 1 k VIN MCP6021 + 1 M IN+ INMCP330X VREF 0.1 F Common Mode Input Range 1 F 1 F VOUT VIN MCP1525 The common mode input range has no restriction and is equal to the absolute input voltage range: VSS -0.3V to VDD + 0.3V. However, for a given VREF, the common mode voltage has a limited swing, if the entire range of the A/D converter is to be used. Figure 6-7 and Figure 6-8 show the relationship between VREF and the common mode voltage swing. A smaller VREF allows for wider flexibility in a common mode voltage. VREF levels, down to 400 mv, exhibit less than 0.1 LSB change in DNL and INL. For characterization graphs that show this performance relationship, see Figure 2-9 and Figure 2-12. VDD = 5V 5 4.05V 2.8V 0.1 F 4 3 2 1 0 -1 0.25 0.95V FIGURE 6-5: Adding an amplifier allows for gain and also buffers the input from any high impedance sources. This circuit shows that some headroom will be lost due to the amplifier output not being able to swing all the way to the rail. An example would be for an output swing of 0V to 5V. This limitation can be overcome by supplying a VREF that is slightly less than the common mode voltage. Using a 2.048V reference for the A/D converter while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure 6-5. Common Mode Range (V) 2.3V 1.0 2.5 4.0 5.0 VREF (V) FIGURE 6-7: Common Mode Input Range of Full Differential Input Signal versus VREF. VDD = 5V 5 4.05V 2.8V VDD = 5V 10 k 1 k VIN MCP606 + 1 M IN+ INMCP330X VREF 10 k 2.048V 0.1 F Common Mode Range (V) 4 3 2 1 0 -1 0.25 1 F 2.3V 0.95V 1 F VOUT VIN MCP1525 0.5 1.25 2.0 2.5 0.1 F VREF (V) FIGURE 6-8: Common Mode Input Range versus VREF for Pseudo Differential Input. FIGURE 6-6: Circuit solution to overcome amplifier output swing limitation. 2002 Microchip Technology Inc. DS21697B-page 19 MCP3302/04 6.5 Buffering/Filtering the Analog Inputs 6.6 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 F is recommended. Digital and analog traces on the board should be separated as much as possible, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors (see Figure 6-10). For more information on layout tips when using the MCP3302/04, or other ADC devices, refer to Application Note 688, "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection 1 F CL VREF IN+ MCP330X VIN 7.86 k 2.2 F MCP601 + 14.6 k 1 F IN0.1 F Inaccurate conversion results may occur if the signal source for the A/D converter is not a low impedance source. Buffering the input will overcome the impedance issue. It is also recommended that an analog filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-9, where an op amp is used to drive the analog input of the MCP3302/04. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Values shown are for a 10 Hz Butterworth Low Pass filter. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLab(R) software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see Application Note 699 "Anti-Aliasing Analog Filters for Data Acquisition Systems". VDD 4.096V Reference 0.1 F MCP1541 10 F Device 4 Device 1 FIGURE 6-9: The MCP601 Operational Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by the MCP3302/04. Device 3 Device 2 FIGURE 6-10: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. DS21697B-page 20 2002 Microchip Technology Inc. MCP3302/04 6.7 Utilizing the Digital and Analog Ground Pins The MCP3302/04 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-11, the analog and digital circuitry are separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10 . If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane, as shown in Figure 6-11. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. VDD MCP3302/04 Digital Side -SPI Interface -Shift Register -Control Logic Substrate 5 - 10 DGND AGND 0.1 F Analog Side -Sample Cap -Capacitor Array -Comparator Analog Ground Plane FIGURE 6-11: Separation of Analog and Digital Ground Pins. 2002 Microchip Technology Inc. DS21697B-page 21 MCP3302/04 7.0 7.1 SERIAL COMMUNICATIONS Output Code Format TABLE 7-1: BINARY TWO'S COMPLEMENT OUTPUT CODE EXAMPLES. Sign Bit 0 0 0 0 0 1 1 1 1 Binary Data Decimal DATA +4095 +4094 +2 +1 0 -1 -2 -4095 -4096 The output code format is a binary two's complement scheme, with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the INinput, the sign bit will be a zero. If the IN- input is higher, the sign bit will be a `1'. The diagram shown in Figure 7-1 shows the output code transfer function. In this diagram, the horizontal axis is the analog input voltage and the vertical axis is the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word is zero. As IN+ gets larger with respect to IN-, the sign bit is a zero and the data word gets larger. The full scale output code is reached at +4095 when the input [(IN+) - (IN-)] reaches VREF - 1 LSB. When IN- is larger than IN+, the two's complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table 7-1. Output Code 0 + 1111 1111 1111 (+4095) 0 + 1111 1111 1110 (+4094) Analog Input Levels Full Scale Positive (IN+)-(IN-)=VREF-1 LSB (IN+)-(IN-) = VREF-2 LSB IN+ = (IN-) +2 LSB IN+ = (IN-) +1 LSB IN+ = ININ+ = (IN-) - 1 LSB IN+ = (IN-) - 2 LSB (IN+)-(IN-) = VREF-2 LSB Full Scale Negative (IN+)-(IN-) = VREF-1 LSB 1111 1111 1111 1111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 Positive Full Scale Output = VREF -1 LSB 0 + 0000 0000 0011 (+3) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0001 (+1) 0 + 0000 0000 0000 (0) IN+ > IN1 + 1111 1111 1111 (-1) 1 + 1111 1111 1110 (-2) 1 + 1111 1111 1101 (-3) -VREF IN+ < IN- VREF Analog Input Voltage IN+ - IN- 1 + 0000 0000 0001 (-4095) Negative Full Scale Output = -VREF 1 + 0000 0000 0000 (-4096) FIGURE 7-1: Output Code Transfer Function. DS21697B-page 22 2002 Microchip Technology Inc. MCP3302/04 7.2 Communicating with the MCP3302 and MCP3304 TABLE 7-2: CONFIGURATION BITS FOR THE MCP3302 Input Configuration single ended single ended single ended single ended differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ Control Bit Selections Single D2* D1 /Diff 1 1 1 1 0 0 0 0 X X X X X X X X 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Communication with the MCP3302/04 devices is done using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 7-2). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single ended or differential input mode. Each channel in single ended mode will operate as a 12-bit converter with a unipolar output. No negative codes will be output in single ended mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 7-2 and Table 7-3 show the configuration bits for the MCP3302 and MCP3304, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. After the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a "don't care" for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 13 clocks will output the result of the conversion with the sign bit first, followed by the 12 remaining data bits, as shown in Figure 7-2. Note that if the device is operating in the single ended mode, the sign bit will always be transmitted as a `0'. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted, and the device continues to receive clocks while the CS is held low, the device will output the conversion result, LSB, first, as shown in Figure 7-3. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 7.3 for more details on using the MCP3302/04 devices with hardware SPI ports *D2 is don't care for MCP3302 TABLE 7-3: Control Bit Selections SinglE /Diff 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CONFIGURATION BITS FOR THE MCP3304 Input Configuration single ended single ended single ended single ended single ended single ended single ended single ended differential differential differential differential differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ CH4 = IN+ CH5 = INCH4 = INCH5 = IN+ CH6 = IN+ CH7 = INCH6 = INCH7 = IN+ D1 D0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2002 Microchip Technology Inc. DS21697B-page 23 MCP3302/04 TSAMPLE TCSH CS TSUCS CLK TSAMPLE DIN Start SGL/ D2 D1 D0 DIFF Don't Care Start SGL/ DIFF D2 DOUT HI-Z Null SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * Bit TCONV TACQ TDATA ** HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure 7-3 below. ** TDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. When operating in single ended mode, the sign bit will always be transmitted as a `0'. FIGURE 7-2: Communication with MCP3302/04 (MSB first Format). TSAMPLE TCSH CS TSUCS CLK Power Down Start DIN D2 D1 D0 SGL/ DIFF Don't Care DOUT HI-Z Null Bit SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB* HI-Z (MSB) TACQ TCONV TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** TDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. When operating in single ended mode, the sign bit will always be transmitted as a `0'. FIGURE 7-3: Communication with MCP3302/04 (LSB first Format). DS21697B-page 24 2002 Microchip Technology Inc. MCP3302/04 7.3 Using the MCP3302/04 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3302 and MCP3304 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending `leading zeros' before the start bit. For example, Figure 7-4 and Figure 7-5 show how the MCP3302/04 devices can be interfaced to a MCU with a hardware SPI port. Figure 7-4 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 7-5 shows the similar case of SPI Mode 1,1, where the clock idles in the `high' state. As shown in Figure 7-4, the first byte transmitted to the A/D Converter contains 6 leading zeros before the start bit. Arranging the leading zeros this way produces the 13 data bits to fall in positions easily manipulated by the MCU. The sign bit is clocked out of the A/D Converter on the falling edge of clock number 11, followed by the remaining data bits (MSB first). After the second eight clocks have been sent to the device, the MCU receive buffer will contain 2 unknown bits (the output is at high impedance for the first two clocks), the null bit, the sign bit and the 4 highest order bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. Figure 7-5 shows the same situation in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. 2002 Microchip Technology Inc. DS21697B-page 25 MCP3302/04 CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D Converter on falling edges DIN Start SGL/ D2 DIFF HI-Z Start Bit 0 ? ? 0 ? 0 ? 0 ? 1 SGL/ DIFF D1 D0 NULL SB BIT Don't Care DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) ? = Unknown Bits X = Don't Care Bits D2 ? D1 ? DO X X X X X X X X X X X X X X X ? ? 0 ? (Null) SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 7-4: idles low). SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D Converter on falling edges DIN Start HI-Z Start Bit 0 0 0 0 1 SGL/ DIFF SGL/ DIFF D2 D1 D0 Don't Care Don't Care DOUT MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) NULL SB B11 B10 B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 D2 D1 DO X X X X X X X X X X X X X X X ? ? ? ? ? ? ? ? ? ? 0 (Null) SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ? = Unknown Bits X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 7-5: idles high). SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK DS21697B-page 26 2002 Microchip Technology Inc. MCP3302/04 8.0 8.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3302-B I/P 0125NNN 14-Lead SOIC (150 mil) Example: MCP3302-B XXXXXXXXXXX 0YWWNNN XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) Example: 3302-C IYWW NNN XXXXXXXX YYWW NNN Please contact Microchip Factory for B-Grade TSSOP devices Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2002 Microchip Technology Inc. DS21697B-page 27 MCP3302/04 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3304) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3304-B I/P YYWWNNN 16-Lead SOIC (150 mil) (MCP3304) Example: MCP3304-B XXXXXXXXXX IYWWNNN XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21697B-page 28 2002 Microchip Technology Inc. MCP3302/04 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2002 Microchip Technology Inc. DS21697B-page 29 MCP3302/04 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 MIN Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21697B-page 30 2002 Microchip Technology Inc. MCP3302/04 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 n B 1 A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 MIN INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 MAX MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 2002 Microchip Technology Inc. DS21697B-page 31 MCP3302/04 16-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n E 1 A A2 c eB A1 B1 B Units Dimension Limits n p INCHES* NOM 16 .100 .140 .155 .115 .130 .015 .300 .313 .240 .250 .740 .750 .125 .130 .008 .012 .045 .058 .014 .018 .310 .370 5 10 5 10 p MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.40 5 10 5 10 L MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .170 Molded Package Thickness A2 .145 Base to Seating Plane A1 Shoulder to Shoulder Width E .325 Molded Package Width E1 .260 Overall Length D .760 Tip to Seating Plane L .135 c Lead Thickness .015 Upper Lead Width B1 .070 Lower Lead Width B .022 Overall Row Spacing eB .430 Mold Draft Angle Top 15 Mold Draft Angle Bottom 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21697B-page 32 2002 Microchip Technology Inc. MCP3302/04 16-Lead Plastic Small Outline (SL) - Narrow 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 16 .050 .053 .061 .052 .057 .004 .007 .228 .237 .150 .154 .386 .390 .010 .015 .016 .033 0 4 .008 .009 .013 .017 0 12 0 12 MILLIMETERS NOM 16 1.27 1.35 1.55 1.32 1.44 0.10 0.18 5.79 6.02 3.81 3.90 9.80 9.91 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.33 0.42 0 12 0 12 A1 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .069 .061 .010 .244 .157 .394 .020 .050 8 .010 .020 15 15 1.75 1.55 0.25 6.20 3.99 10.01 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108 2002 Microchip Technology Inc. DS21697B-page 33 MCP3302/04 NOTES: DS21697B-page 34 2002 Microchip Technology Inc. MCP3302/04 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 013001 Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2002 Microchip Technology Inc. DS21697B-page 35 MCP3302/04 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: MCP3302/04 Questions: 1. What are the best features of this document? Y N Literature Number: DS21697B FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS21697B-page 36 2002 Microchip Technology Inc. MCP3302/04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Grade X Temperature Range /XX Package Examples: a) b) Device: MCP3302: MCP3302T: MCP3304: MCP3304T: B C I P SL ST 13-Bit Serial A/D Converter 13-Bit Serial A/D Converter (Tape and Reel) 13-Bit Serial A/D Converter 13-Bit Serial A/D Converter (Tape and Reel) MCP3302-BI/P: 1 LSB INL, Industrial Temperature, PDIP package MCP3302-BI/SL: 1 LSB INL, Industrial Temperature, SOIC package MCP3302-CI/ST: 2 LSB INL, Industrial Temperature, TSSOP package MCP3304-BI/P: 1 LSB INL, Industrial Temperature, PDIP package MCP3304-BI/SL: 1 LSB INL, Industrial Temperature, SOIC package c) a) Grade: = 1 LSB INL = 2 LSB INL = -40C to +85C b) Temperature Range: Package: = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21697B-page37 MCP3302/04 NOTES: DS21697B-page 38 2002 Microchip Technology Inc. MCP3302/04 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21697B-page 39 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. 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Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 05/16/02 DS21697B-page 40 2002 Microchip Technology Inc. |
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